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1/17 tda7440 april 2010 1 features ? input multiplexer ? 4 stereo inputs ? selectable input gain for optimal adaptation to different sources ? one stereo output ? treble and bass control in 2.0db steps ? volume control in 1.0db steps ? two speaker attenuators: ? two independent speaker control in 1.0db steps for balance facility ? independent mute function ? all function are programmable via serial bus 2 description the tda7440d is a volume tone (bass and treble) balance (left/right) processor for quality audio applications in hi-fi systems. selectable input gain is pr ovided. control of all the functions is accomplished by serial bus. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are obtained tone control digitally controlled audio processor figure 2. block diagram 0/30db 2db step muxoutl inl volume volume treble treble treble(l) muxoutr inr treble ( r ) bout(l) spkr att left lout scl sda dig_gnd rout d98au883 i 2 cbus decoder + latches 100k 100k 100k 100k g l-in1 l-in2 l-in3 l-in4 100k 100k 100k 100k r-in1 r-in2 r-in3 r-in4 g input multiplexer + gain bass bin(l) bass spkr att right bout ( r ) bin ( r ) supply cref agnd v s 27 4 5 6 7 3 2 1 28 21 22 20 26 24 25 10 11 19 12 13 23 8 9 18 14 15 r b r b v ref fi gure 1. p ac k age table 1. order codes order code package tda7440d so-28 tda7440d013tr tape & reel so-28 rev. 4
tda7440 2/17 figure 3. pin connection (top view) table 2. absolute maximum ratings table 3. thermal data table 4. quick reference data symbol parameter value unit v s operating supply voltage 10.5 v t amb operating ambient temperature 0 to 70 c t stg storage temperature range -55 to 150 c symbol parameter value unit r th j-pin thermal resistance junction-pins 85 c/w symbol parameter min. typ. max. unit v s supply voltage 6 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db input gain in (2db step) 0 30 db volume control (1db step) -47 0 db treble control (2db step) -14 +14 db bass control (2db step) -14 +14 db balance control 1db step -79 0 db mute attenuation 100 db l_in3 l_in4 muxoutl in(l) muxout(r) bin(r) in(r) bout(r) bin(l) 1 3 2 4 5 6 7 8 9 bout(l) n.c. n.c. treble(r) treble(l) scl sda dig-gnd cref 23 22 21 20 19 17 18 16 15 d98au884 10 11 12 13 14 28 27 26 25 24 r_in3 r_in2 r_in1 l_in1 l_in2 v s agnd rout lout r_in4
3/17 tda7440 table 5. electrical characteristcs refer to the test circuit t amb = 25c, v s = 9v, r l = 10k ? , r g = 600 ? , all controls flat (g = 0db), unless otherwise specified. symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10.2 v i s supply current 4 7 10 ma svr ripple rejection 60 90 db input stage r in input resistance 70 100 130 k ? v cl clipping level thd = 0.3% 2 2.5 vrms s in input separation the selected input is grounded through a 2.2 capacitor 80 100 db g inmin minimum input gain -1 0 1 db g inman maximum input gain 29 30 31 db g step step resolution 1.5 2 2.5 db volume control r i input resistance 20 33 50 k ? c range control range 45 47 49 db a vmax max. attenuation 45 47 49 db a step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -24db -1.0 0 1.0 db a v = -24 to -47db -1.5 0 1.5 db e t tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 0 2 db v dc dc step adjacent attenuation steps from 0db to a v max 0 0.5 3mv mv a mute mute attenuation 80 100 db bass control (1) gb control range max. boost/cut +12.0 +14.0 +16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 33 44 55 k ? treble control (1) gt control range max. boost/cut +13.0 +14.0 +15.0 db t step step resolution 1 2 3 db speaker attenuators c range control range 70 76 82 db s step step resolution 0.5 1 1.5 db e a attenuation set error a v = 0 to -20db -1.5 0 1.5 db a v = -20 to -56db -2 0 2 db v dc dc step adjacent attenuation steps 0 3 mv a mute mute attenuation 80 100 db note1: 1) the device is functionally good at vs = 5v. a step down, on vs, to 4v does?t reset the device. 2) bass and treble response: the center frequency and the response quality can be chosen by the external circuitry.
tda7440 4/17 figure 4. test circuit audio outputs v clip clipping level d = 0.3% 2.1 2.6 vrms r l output load resistance 2 k ? r o output impedance 10 30 50 ? v dc dc voltage level 3.5 3.8 4.1 v general e no output noise all gains = 0db; 5 15 v bw = 20hz to 20khz flat e t total tracking error a v = 0 to -24db 0 1 db a v = -24 to -47db 0 2 db s/n signal to noise ratio all gains 0db; v o = 1vrms 95 106 db s c channel separation left/right 80 100 db ddistortion a v = 0; v i = 1vrms 0.01 0.08 % bus input v il input low voltage 1v v ih input high voltage 3 v i in input current v in = 0.4v -5 0 5 a v o output voltage sda acknowledge i o = 1.6ma 0.4 0.8 v table 5. electrical characteristcs (continued) refer to the test circuit t amb = 25c, v s = 9v, r l = 10k ? , r g = 600 ? , all controls flat (g = 0db), unless otherwise specified. symbol parameter test condition min. typ. max. unit 10 f 5.6nf 100nf 100nf 5.6k 2.2 f 5.6nf 2.2 f 100nf 100nf 5.6k 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0.47 f 0/30db 2db step muxoutl inl volume volume treble treble treble(l) muxoutr inr treble(r) bout(l) spkr att left lout scl sda dig_gnd rout d98au885 i 2 cbus decoder + latches 100k 100k 100k 100k g l-in1 l-in2 l-in3 l-in4 100k 100k 100k 100k r-in1 r-in2 r-in3 r-in4 g input multiplexer + gain bass bin(l) bass spkr att right bout(r) bin(r) supply cref agnd v s 27 4 5 6 7 3 2 1 28 21 22 20 26 24 25 10 11 19 12 13 23 8 9 18 14 15 r b r b v ref
5/17 tda7440 3 application suggestions the first and the last stages are volume control blocks. the control range is 0 to -47db (mute) for the first one, 0 to -79db (mute) for the last one. both of them have 1db step resolution. the very high resolution allows the implementation of systems free from any noisy acoustical effect. the tda7440d audioprocessor pr ovides 3 bands tones control. 3.1 bass stage several filter types can be implemented, connecting external components to the bass in and out pins. the fig.5 refers to basic t type bandpass filter starting from the filter component values (r1 internal and r2,c1,c2 external) the centre frequency fc, the gain av at max. boost and the filter q factor are computed as follows: viceversa, once fc, av, and ri inte rnal value are fixed, the exte rnal components values will be: figure 5. treble stage the treble stage is a high pass filter whose time constant is fixed by an internal resistor (25k ? typical) and an external capacitor connected bet ween treble pins and ground. typical responses are reported in figg. 14 to 17. cref the suggested 10mf reference capacitor (cref) value can be reduced to 4.7mf if the application re- quires faster power on. f c 1 2 r1 r2 c1 c2 ??? ?? ----------------------------------------------------------------- = a v r2 c2 r2 c1 r i c1 + + r2 c1 r2 c2 + --------------------------------------------------------------- - = q r1 r2 c1 c2 ??? r2 c1 r2 c2 + ------------------------------------------------- - = c1 a v 1 ? 2 f c r i q ?? ? ? ----------------------------------------- - c2 q 2 c1 ? a v 1 ? q 2 ? ----------------------------- - r2 a v 1 ? q 2 ? 2 c1 f c a v 1 ? () q ?? ? ? ? ---------------------------------------------------------------------- - = = = ri internal c 2 out in c 1 r 2 d95au313
tda7440 6/17 figure 6. thd vs. frequency figure 7. thd vs. r load figure 8. channel separation vs. frequency figure 9. bass response figure 10. treble responsey r i = 44k ? c9 = c10 = 100nf (bout, bin) r3 = 5.6k ?
7/17 tda7440 4i 2 c bus interface data transmission from microprocessor to the tda7440d and vice versa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). 4.1 data validity as shown in fig. 11, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 4.2 start and stop conditions as shown in fig. 12 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transi tion of the sda line while scl is high. 4.3 byte format every byte transferred on the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 4.4 acknowledge the master ( p) puts a restive high level on the sda line during the acknowledge clock pulse (see fig. 13). the peripheral (audio processor) that acknowledges has to pull-down (low) the sda line during this clock pulse. the audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. 4.5 transmission without acknowledge avoiding to detect the acknowledge of the audio processor, the p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 11. data validity on the i 2 cbus figure 12. timing diagram of i 2 cbus figure 13. acknowledge on the i 2 cbus sda scl data line stable, data valid change data allowed d99au1031 scl sda start i 2 cbus stop d99au1032 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033
tda7440 8/17 5 software specification interface protocol the interface protocol comprises: ? a start condition (s) ? a chip address byte, containing the tda7440d ? a subaddress bytes ? a sequence of data (n byte + acknowledge) ? a stop condition (p) ack = acknowledge s = start p = stop a = address b = auto increment 5.1 examples 5.1.1 no incremental bus the tda7440d receives a start condition, the correct chip address, a subaddress with the b = 0 (no in- cremental bus), n-datas (all these data concern the subaddress selected), a stop condition. 5.1.2 incremental bus the tda7440d receive a start conditions, the correct chip address, a subaddress with the b = 1 (incre- mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "xxx1000" to "xxx111 1" of data are ignored. the data 1 concern the subaddress sent, and the da ta 2 concerns the subaddr ess sent plus one sent in the loop etc, and at the end it receivers the stop condition. s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au420 x data subaddress data 1 to data n x x b s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au421 x d3 subaddress data x x 0 d2 d1 d0 s 1 0 0 0 1 0 0 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au422 x d3 subaddress data 1 to data n x x 1 d2 d1 d0
9/17 tda7440 5.2 power on reset condition table 6. 5.3 data bytes address = 88 hex (addr:open). table 7. function selection: first byte (subaddress) b = 1: incremental bus active b = 0: no incremental bus x = don?t care in incremental bus mode, the "not used" function must be addressed in any case. for example to refresh "volume = 0db" and speaker_r = -40db", the following bytes must be sent: table 8. table 9. input selection input selection in2 input gain 28db volume mute bass 0db treble 2db speaker mute msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 x x x b 0 0 0 0 input select xxxb0 0 0 1input gain xxxb0 0 1 0volume xxxb0 0 1 1bass xxxb0 1 0 0not used xxxb0 1 0 1treble x x x b 0 1 1 0 speaker attenuate "r" x x x b 0 1 1 1 speaker attenuate "l" subaddress xxx10010 volume data x0000000 bus data xxxx1111 not used data xxxx1111 treble data xxxx1111 speaker_r data x0000010 msb lsb input multiplexer d7 d6 d5 d4 d3 d2 d1 d0 xxxxxx0 0 in4 xxxxxx0 1 in3 xxxxxx1 0 in2 xxxxxx1 1 in1
tda7440 10/17 5.3 data bytes (continued) table 10. input gain selection gain = 0 to 30db table 11. volume selection volume = 0 to 47db/mute msb lsb input gain d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0000 0db 0001 2db 0010 4db 0011 6db 0100 8db 0 1 0 1 10db 0 1 1 0 12db 0 1 1 1 14db 1 0 0 0 16db 1 0 0 1 18db 1 0 1 0 20db 1 0 1 1 22db 1 1 0 0 24db 1 1 0 1 26db 1 1 1 0 28db 1 1 1 1 30db msb lsb volume d7 d6 d5 d4 d3 d2 d1 d0 1db steps 000 0db 001 -1db 010 -2db 011 -3db 100 -4db 101 -5db 110 -6db 111 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db x111xxx mute
11/17 tda7440 5.3 data bytes (continued) table 12. bass selection table 13. treble selection msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db msb lsb treble d7 d6 d5 d4 d3 d2 d1 d0 2db steps 0 0 0 0 -14db 0 0 0 1 -12db 0 0 1 0 -10db 0011 -8db 0100 -6db 0101 -4db 0110 -2db 0111 0db 1111 0db 1110 2db 1101 4db 1100 6db 1011 8db 1 0 1 0 10db 1 0 0 1 12db 1 0 0 0 14db
tda7440 12/17 5.3 data bytes (continued) table 14. speaker attenuate selection msb lsb speaker attenuation d7 d6 d5 d4 d3 d2 d1 d0 1db 0 0 0 0db 0 0 1 -1db 0 1 0 -2db 0 1 1 -3db 1 0 0 -4db 1 0 1 -5db 1 1 0 -6db 1 1 1 -7db 0000 0db 0001 -8db 0 0 1 0 -16db 0 0 1 1 -24db 0 1 0 0 -32db 0 1 0 1 -40db 0 1 1 0 -48db 0 1 1 1 -56db 1 0 0 0 -64db 1 0 0 1 -72db 1111xxx mute
13/17 tda7440 figure 14. pins: 23 figure 15. pins: 26, 27 figure 16. pins: 1, 2, 3, 4, 5, 6, 7, 28 figure 17. pins: 8, 10 figure 18. pins: 19, 11 figure 19. pins: 12, 14 20k 20k cref v s d96au430 v s v s d96au434 20 a rout 24 lout 20 a v s 100k v ref d96au425 in v s d96au426 20 a v s mixout gnd 20 a v s 33k d96au427 inl inr v ref 44k v s bin(r) d96au428 20 a bin(l)
tda7440 14/17 figure 20. pins: 13, 15 figure 21. pins: 18, 19 figure 22. pin: 20 figure 23. pin 21 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade defi- nitions and product status are available at: www.st.com . ecopack ? is an st trademark. 44k v s bout ( r ) d96au429 20 a bout(l) 50k v s treble(r) d96au433 20 a treble(l) d96au424 20 a scl d96au423 20 a sda
15/17 tda7440 figure 24. so-28 mechanical data & package dimensions so-28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data
tda7440 16/17 7 revision history table 15. revision history date revision description of changes january 2004 2 first issue june 2004 3 modified the style-sheet in comp liance with the last revision of the ?corporate technical pubblications design guide?. 30-apr-2010 4 updated title and added envir onmental compliance statement for package
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